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Display Driver IC Engineer (Pixel Pipeline)

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Display Driver IC Engineer (Pixel Pipeline)
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Sunnyvale, CA
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Meta Reality Lab is the world leader in the design of virtual and augmented reality systems. Come work alongside expert engineers and research scientists to create the technology that makes VR pervasive and universal. Join the adventure of a lifetime as we make science fiction real and change the world. The Display Architecture Team within the VR organization is seeking a Display Driver IC Engineer to lead the implementation of Meta’s proprietary display IP for VR displays. As a member of the VR Display Team, the successful candidate will be working closely with Display Driver IC (DDIC) architects, Visual Quality team, and DDIC vendors to design, evaluate performance, and embed Meta’s proprietary visual quality IP within the vendor's DDIC for future VR products. This role offers involvement in a mix of forward-looking and product-critical projects, and requires close collaboration with multiple teams within the Meta Reality Labs.
Display Driver IC Engineer (Pixel Pipeline) Responsibilities
  • Define hardware architecture of proprietary display IP for VR displays in collaboration with display algorithm architects.
  • Design and implement the algorithm in Verilog with optimized gate-count, meeting performance targets.
  • Collaborate with DDIC vendors to ensure consistency between IP architecture and the DDIC design.
  • Collaborate with vendors to embed IP within the vendor’s DDIC. Supervise chip-level verification.
  • Participate in DDIC design reviews with vendors and assess overall digital design flow including verification coverage, clock synthesis, timing signoff.
  • Collaborate with the system team to bring up and test the algorithm for production readiness.
Minimum Qualifications
  • Masters Degree in Electrical Engineering, Computer Science, or equivalent work experience.
  • 10+ years of industry work experience in the field of IC design and development.
  • Understanding of the front-end digital design flow: RTL design, logic synthesis, timing verification.
  • Understanding of pixel pipeline for Displays and DDIC architecture.
  • Experience with at least one programming language such as Matlab, Python or C++.
  • Effective communication skills.
Preferred Qualifications
  • Ph.D. in Electrical Engineering.
  • Hands-on experience with FPGA prototyping for display applications.
  • Experience with architecture and design of display IP such as sub-pixel rendering, foveation, Mura, burn-in compensation algorithms.
  • Familiar with compression IP design such as DSC.
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About Meta
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or sincerely held religious beliefs, or who are neurodivergent or require pregnancy-related support. If you need support, please reach out to accommodations-ext@fb.com.
$170,000/year to $240,000/year + bonus + equity + benefits

Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base salary, Meta offers benefits. Learn more about benefits at Meta.
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